Optimization, Analysis and Comparison of Two Stage and Three Stage Operational Amplifiers using 0.3µM Process Technology for SCMOS

Author(s):

Arpita Johari , SIRT; Minal Saxena, SIRT

Keywords:

Operational Amplifiers, CMOS, Quiscent Point analysis, Operating Point, AC and DC analysis

Abstract:

A Design presented in this work is a two stage and three stage or multistage CMOS operational amplifiers and frequency analysis of the same is also done and analyze the effect of various parameters on the characteristics of operational amplifier, which operates at 5V power supply using C5 process CMOS technology. Here parameters are computed and response curves are computed between all characteristics such as Gain, PM, GBW, Slew Rate etc using AC, DC and transient characteristics of it. The operational amplifier, design is a two-stage, three-stage, multi-stage CMOS operational amplifier. The design and simulations are carried out to achieve these values approximately. Design will be carried out in Electric CAD and LTSpice. Simulation results are verified using LTSpice. There is numerous numbers of configurations for operational amplifier exists in literature. The classification of the namely existing topologies includes single stage, two stage, three stage and multistage amplifiers. A Pad frame is also designed for a three stage topology operational amplifier DRCs and network consistency checks verified through the design using 300 nm for SCMOS. By results and reasons two stage and three stage topologies are suitable choices for low voltage and high performance applications. The presented architecture will also define the operating characteristics of Operational Amplifiers; a brief comparison is also presented for operating point analysis for multiple stage operational amplifiers. FFT analysis is also done for better noise index results.

Other Details:

Manuscript Id	:	IJSTEV2I11130
Published in	:	Volume : 2, Issue : 11
Publication Date	:	01/06/2016
Page(s)	:	567-575

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