Analysis & Design of low Power Dynamic latched Double-Tail Comparator

Author(s):

Manish Kumar , Indus Institute of Engineering and Technology, Kinana, Jind, Haryana, India - 126102; Kapil Sachdeva, Indus Institute of Engineering and Technology, Kinana, Jind, Haryana, India - 126102

Keywords:

CMOS technology, MOSFET, Dynamic Latched Comparator

Abstract:

The need for low power, high speed Analog-To-Digital converters is pushing towards the use of dynamic comparator to maximize speed &power efficiency. In this paper, we designed a Dynamic Latched Double-Tail Comparator which is used in implementation of many ADC’s. An analysis on the delay of the comparator will presented. Simulation results in 0.18um CMOS technology confirm the analysis results. The main idea of this Dynamic Latched Comparator is to reduce the static power consumption by completely cutoff the leakage current to ground. For this purpose, the Power Gating technique is used. The frequency of this comparator is 1GHz at supply voltage of 1.8V.

Other Details:

Manuscript Id	:	IJSTEV2I11298
Published in	:	Volume : 2, Issue : 11
Publication Date	:	01/06/2016
Page(s)	:	822-826

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