Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating

Ranjana Yadav; Alka Agrawal

CALL FOR PAPERS : Feb-2026

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25-Feb-26

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Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating

Author(s):

Ranjana Yadav , Hindustan College of Science & Technology; Alka Agrawal, Hindustan College of Science & Technology

Keywords:

MTCMOS technique, Johnson Counter, Clock Gating

Abstract:

To minimize Power dissipation is one of the major concerns in recent VLSI designing. As technology is growing our chip size is getting reduced and many other micro-electronics reliabilities are growing slowly, minimum power designing of any system has become priority. Computer system consists of sequential circuits mostly and that is why efficient low power design of various sequential circuits is very important. In this paper, we have proposed a low power design scheme of Johnson Counter using MTCMOS technique. Doing some power analysis, it is considered that our proposed system has lower power dissipation and power delay product as compared to the conventional design.