FPGA Implementation of High Speed Floating Point Mutliplier using Log Based Design

Author(s):

Kanika Bhardwaj , Ideal College of Engineering & Technology, Ghaziabad; Juhi Jain, Ideal College of Engineering & Technology, Ghaziabad; Rakhi, Ideal College of Engineering & Technology, Ghaziabad

Keywords:

FPU, Floating Point Multiplier, FPGA Implementation

Abstract:

Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. Multiplication of floating point numbers found extensive use in DSP applications involving huge range. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay. The proposed log based Floating point Multiplier is designed using Verilog HDL and targeted on Spartan 6 FPGA.

Other Details:

Manuscript Id	:	IJSTEV3I11091
Published in	:	Volume : 3, Issue : 11
Publication Date	:	01/06/2017
Page(s)	:	366-369

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