Low Voltage and Low Power in SRAM Read and Write Assist Techniques

Dipti Choudhary; Vipul Bhatnagar

CALL FOR PAPERS : Feb-2026

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25-Feb-26

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Low Voltage and Low Power in SRAM Read and Write Assist Techniques

Author(s):

Dipti Choudhary , Inderprastha Engineering College; Vipul Bhatnagar, Inderprastha Engineering College

Keywords:

Assist Technique, SRAM, Write Assist, Write Margin

Abstract:

In this paper, various SRAM write assist techniques like VDD lowering, VSS raising, word-line boosting, negative bit line approach on standard 6T cell are compared with WSNM, RSNM, VDD, temperature. 10T TGA SRAM cell is compared with their VDD (supply voltage), WSNM (Write static noise margin), RSNM (Read static noise margin) with write assist techniques on it and used temperature variation as well. And one new write assist technique is proposed in this paper i.e, Boosted Negative Bit Line Approach and implemented on 10T TGA SRAM cell. In this technique we try to improve write features and read simultaneously. And also compared 6T, 8T and 10T SRAM cells for read assist. Simulations have been performed in Tanner EDA 32 nm CMOS technology.