Self-Resetting Logic in VLSI Circuits: A Review

Author(s):

Shivani Kulshrestha , SACHDEVA INSTITUTE OF TECHNOLOGY, MATHURA; Vikas Kumar Rai, SACHDEVA INSTITUTE OF TECHNOLOGY, MATHURA

Keywords:

SRL. GDI, Dynamic CMOS Logic. PTL

Abstract:

This paper presents a thorough study on the Self Resetting logic for the power reduction in VLSI circuits solving several problems in dynamic CMOS circuits. The CMOS technology has brought the revolution to the voltage scaling and transistor sizing since many years as it has been the perfect choice of VLSI designers to reduce the power and delay in any VLSI circuit. But, when the large number of PMOS transistors end up with the higher input loads it dissipates enormous power resulting into introducing itself as a power sinking circuitry system. Sometimes, the power dissipation is more due to the high operating frequency as well. There plays an important role the PTL (Pass Transistor Logic) circuit providing the better characteristics. This PTL logic is said to be dynamic CMOS logic and hence been used for the high speed applications due to its better performance. The CMOS dynamic logic is further enveloped with some drawbacks such as charge sharing, charge leakage, loss of noise immunity and timing problems etc. due to which there was a need of introduction of Self Resetting Logic (SRL).

Other Details:

Manuscript Id	:	IJSTEV3I2089
Published in	:	Volume : 3, Issue : 2
Publication Date	:	01/09/2016
Page(s)	:	234-237

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