Implementation of Two Parallel FIR Filter Structure Using LUT less DA

Author(s):

vamshi krishna alle , srm university; e. chitra, srm university

Keywords:

Two parallel FIR filter, LUT less Distributed arithmetic (DA), Finite Impulse Response (FIR), Symmetric coefficients

Abstract:

This paper describes the implementation of two parallel FIR filter based on traditional method costs considerable hardware area and power. The FIR filters mainly contain the delay elements, adders and multipliers. The usage of multipliers in the filter structure leads to two drawbacks; they are (i) increase in area and (ii) increase in delay which may results ultimately in low speed and performance. A new design and implementation of two parallel FIR filter structure using LUT (Look Up Table) less Distributed Arithmetic (DA) is proposed in this paper which are beneficial to symmetric coefficients reducing half of the multipliers in sub filter blocks of two parallel FIR filter. The LUT less method is used to decrease the amount of required memory units in the two parallel filter structures. In proposed structure, the multipliers are replaced with shifters and adders so that adders weight less than multipliers in terms of silicon area. The overweigh from the additional adders in preprocessing and post processing blocks stay fixed along with the filter length and they doesn’t increase with tap length, this is the key merit of FIR filter architectures. Overall, the synthesis result shows that the proposed two parallel FIR structure can save more than 50 percent of significant area and power of circuit scale and can be applied to different types of filters with different coefficients for its flexibility and high reliability.

Other Details:

Manuscript Id	:	IJSTEV1I10111
Published in	:	Volume : 1, Issue : 10
Publication Date	:	01/05/2015
Page(s)	:	269-274

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