Design of Low Power Pulse Triggered Flip-Flops
Author(s):
Sadhana Patil , Dr. D.Y.Patil School of Engineering, Lohegaon,Pune; Prof. Anil Wanare, Dr. D.Y.Patil School of Engineering, Lohegaon,Pune
Keywords:
Flip-Flop, latch, power, and pulse triggered
Abstract:
In digital CMOS design, power consumption has been a major concern for the past several years. Advanced IC fabrication technology allows the use of nano-scaled devices; so the power dissipation becomes the major problem. Flip-flops are widely used in many sequential logic circuits such as registers, memory elements, counters, etc. These circuits are widely used in the implementation of VLSI chips. Therefore the power consumption of such circuits should be improved, without deteriorating other characteristics. Pulse-triggered FF has a simple circuit which lowers the power consumption of the clock tree system. A P-FF consists of a pulse generator for strobe signals and a latch for data storage. If the triggering pulses are narrow, then the latch acts like an edge-triggered FF.
Other Details:
| Manuscript Id | : | IJSTEV1I10142
|
| Published in | : | Volume : 1, Issue : 10
|
| Publication Date | : | 01/05/2015
|
| Page(s) | : | 203-208
|
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