DESIGN AND ANALYSIS OF LOW VOLTAGE LOW DROPOUT REGULATOR

Author(s):

Ms. Yogeshree Patil , Dr. D. Y. Patil School of Engineering; Prof. S. N. Kulkarni, Dr. D. Y. Patil School of Engineering

Keywords:

Low-dropout (LDO) regulator, low-voltage, Low Quiescent Current, Power Supply Rejection Ratio, Area, 45nm CMOS Technology etc.

Abstract:

In battery operated portable devices, handheld devices and noise sensitive devices which need high precision supply voltages has fuelled the expansion of Low Drop-Out Regulators. Low-Voltage Low-Dropout(LDO) Voltage Regulator that can operate with a very small Input–Output Differential Voltage with nm CMOS technology which improves package density. Now-a-days, design of Low Drop-Out Regulators with high performance is challenging problem. The demand of LDO is increasing because of growing demand of portable electronic devices like cellular phones, pagers, camera recorders and laptops. In this paper, Design and Analysis of Low Voltage Low Dropout Regulator is proposed. The proposed circuit is simulated using 45 nm CMOS technology process parameters and the simulation results are presented. The simulation of proposed circuit is designed using ADS i.e. Advance Design System tool. The proposed LDO gives output voltage near about 0.8V from a 1V supply, and dropout voltage near about 200mV using a reference voltage of 0.4V.

Other Details:

Manuscript Id	:	IJSTEV1I10158
Published in	:	Volume : 1, Issue : 10
Publication Date	:	01/05/2015
Page(s)	:	255-258

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