AN EFFICIENT LOW POWER STAR TOPOLOGY BASED NOC ROUTER ARCHITECTURE DESIGN

P.M.Poongodi; D.Kesavan

CALL FOR PAPERS : Feb-2026

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25-Feb-26

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AN EFFICIENT LOW POWER STAR TOPOLOGY BASED NOC ROUTER ARCHITECTURE DESIGN

Author(s):

P.M.Poongodi , Christian College of Engineering and Technology Oddanchatram, Tamilnadu-624619, India; D.Kesavan, Christian College of Engineering and Technology Oddanchatram, Tamilnadu-624619, India

Keywords:

Low Power, Low Latency, STAR Topology NOC, Hop To Hop Data Transfer Technique

Abstract:

Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communication requirements in digital systems. Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many core systems. VLSI technology is to modify NOC internal router arrangements, shortest path allocation process and neighbor router estimation control. In existing paper the proposed design of 4*4 mesh topology based router architecture and to optimize the path allocation process using hybrid scheme which consist of VCS, CS,PS technique for path allocation work. This work is to reduce the data transferring time between source and destination. The existing system is consuming more power and to increase the circuit complexity level. Our proposed work is to design a 4*4 star topology based network on chip architecture. This work is to reduce the path allocation process using hop to hop data transfer technique. This technique is to increase NOC architecture performance level. This proposed architecture is to optimize the internal connectivity level and to reduce path allocation process level. This technique is to reduce data transfer time between source and destination. The proposed system is used to reduce the latency level and to improve throughput value.