Single Stage and Two Stage OP-AMP Design in 180NM CMOS Technology
Author(s):
ANAND KASUNDRA , DSTC JUNAGADH; Jaydip Ravia, DSTC-JUNAGADH; Chetan Bhetariya, DSTC-JUNAGADH; Himat Chavada, DSTC-JUNAGADH; Rajesh Choravada, DSTC-JUNAGADH
Keywords:
Operational Amplifier (OP-AMP), Complementary MOS (CMOS), Transistor logic (TTL). Metal oxide semiconductor (MOS), Common Mode Rejection Ratio(CMRR)
Abstract:
This paper presents the well define method for the design of single stage and two stage Op–amp in 180nm CMOS process. We have simulated diode connected load with two more PMOS to overcome trade-off between the output voltage swing, the voltage gain, and the input CM range. The operational amplifier has high gain, high input impedance and low output impedance. We have designed two stage op-amp of gain 72dB, CMRR 77dB, slew rate 133V/µs PSRR 57dB. Phase-margin 51˚.Design simulation has been carried out in NGSPICE.
Other Details:
| Manuscript Id | : | IJSTEV2I10125
|
| Published in | : | Volume : 2, Issue : 10
|
| Publication Date | : | 01/05/2016
|
| Page(s) | : | 514-520
|
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