Implementation of RISC Microprocessor for DSP Systems

Author(s):

Poojalaxmi Chikodi , Center for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India; Dr. Meghana Kulkarni, Center for PG Studies, Visvesvaraya Technological University, Belagavi, Karnataka, India

Keywords:

Reduced instruction set computer(RISC), Digital Signal Processor (DSP), Fast Fourier Transform(FFT), Discrete wavelet transform(DWT), VHDL

Abstract:

This paper is about the reduced instruction set computer (RISC), microprocessor CPU design that flavors a smaller and simpler set of instruction. In this project we have described 16-bit pipelined RISC processor for applications such as in real time digital signal processor and embedded systems. The processor designed specifically for DSP systems such as FFT, DWT, Convolution and ALU, executes most of instructions in a single cycle; conventional processors usually performs only arithmetic and mathematical operations. Hence RISC processors have complex control system which requires more clock cycle to operate, thus we overcome this problem using pipelined architecture of 4 stages i.e fetch, decode, execute and write back. In fact compared to base paper the area is reduced and speed is increased. The Simulation is done on XILINX 14.5i tool, implemented on SPARTAN-6 kit. Over all speed is achieved and results are verified.

Other Details:

Manuscript Id	:	IJSTEV2I12243
Published in	:	Volume : 2, Issue : 12
Publication Date	:	01/07/2016
Page(s)	:	536-540

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