Modified Leakage Reduction Circuit Using Self Biasing Circuit

Author(s):

Jerin Varghese Jackson , Saintgits College of Engineering; Abraham .K. Thomas, Saintgits college of Engineering; Susan Abe, Saintgits college of Engineering

Keywords:

Leakage Current, Stacked Transistors, Self Biasing Circuit

Abstract:

The MOSFET design was first introduced in 1960. Since then leakage current is a factor that have been a problem faced by the designers. Leakage current is a phenomenon that usually occurs in a semiconductor in which the mobile carriers flow through an insulated region. Leakage current causes extra consumption of power and larger power consumption may cause failure of the circuit. In this project in order to reduce the leakage current in logic circuits the method adopted is based on a self biasing circuit. In this method conventional techniques of transistor stacking is used. More the number of transistors used for the stacking, more will be the amount of leakage current reduced. Self biasing circuit is provided to reduce the delay and overall power consumption.. Simulation of the circuit shows that along with the leakage current reduction, delay between input and output, power consumption were reduced compared to existing conventional techniques

Other Details:

Manuscript Id	:	IJSTEV2I4081
Published in	:	Volume : 2, Issue : 4
Publication Date	:	01/11/2015
Page(s)	:	303-311

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