Design and Implementation of Testable Reversible Universal Shift Register

Author(s):

Parasurama , VTU MACCHE BELAGUM; Prof. Dr. Meghana Kulkarni, vtu

Keywords:

Flip-Flop, Multiplexer, Reversible Logic, Reversible Gate, Shift Register, Quantum Cost, Garbage Output

Abstract:

The design of testable universal shift register based on conservative logic is tested for unidirectional stuck-at faults by using two test vectors i.e. all 1’s and 0’s. The important memory element in family of sequential circuits is Universal Shift Register. In this project design of sequential application circuits like Universal Shift Register is done by using reversible gates such as Fredkin, Feynman and Peres gates. The proposed 4*4 reversible universal shift register can identify single missing line stuck at faults in the circuits and also it reduces the quantum cost, delay and garbage outputs as well as testability. The important memory element in family of sequential circuits is Universal Shift Register. In this project design of sequential application circuits like Universal Shift Register is done by using reversible gates such as Fredkin, Feynman and Peres gates. The design of testable universal shift register based on conservative logic is tested for unidirectional stuck-at faults by using two test vectors i.e. all 1’s and 0’s. The proposed 4*4 reversible universal shift register can identify single missing line stuck at faults in the circuits and also it reduces the quantum cost, delay and garbage outputs as well as testability.

Other Details:

Manuscript Id	:	IJSTEV3I1039
Published in	:	Volume : 3, Issue : 1
Publication Date	:	01/08/2016
Page(s)	:	108-114

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