Realization of multiplier architecture based on VHBCSE algorithm for reconfigurable FIR filter Using Verilog HDL

Yasmeen; Litty Mathew

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25-Feb-26

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Realization of multiplier architecture based on VHBCSE algorithm for reconfigurable FIR filter Using Verilog HDL

Author(s):

Yasmeen , P.A College of engineering, Mangalore, Karnataka; Litty Mathew, P.A College of engineering, Mangalore, Karnataka

Keywords:

BCSE algorithm, Reconfigurable FIR Filter, SDR system, Shift and add technique, VLSI design

Abstract:

FIR filter with reconfigurability is the significant component in the advanced SDR (software defined radio) application. Complexity and power consumptions are the two factors that must be consider while designing re-configurable fir filter. Proposed VHBCSE algorithm searches for 2-bit CSE vertically across adjacent coefficients at first. Then variable 4bit and 8 bit CSE is applied horizontally within the each coefficient. The VHBCSE algorithm based multiplier design reduces number of adders and switching activity of the multiplier adder block. A 4 tap FIR filter is implemented and the design shows that VHBCSE algorithm based multiplier gives better performance and reduced power consumption and area compared to that of existing fixed 2bit and 3 bit BCSE technique. The design for reconfigurable fir filter based on VHBCSE algorithm is coded in Verilog, synthesized and simulated in Xilinx ISE Design Suite 14.7 tool.