Implementation of High Speed and Energy-Efficient Carry Skip Adder using Verilog HDL

Ubaidulla; Prof. Asia Hazareena

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25-Feb-26

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Implementation of High Speed and Energy-Efficient Carry Skip Adder using Verilog HDL

Author(s):

Ubaidulla , P. A College of Engineering, Mangalore; Prof. Asia Hazareena, P. A College of Engineering, Mangalore

Keywords:

Carry Skip Adder (CSKA), Energy Efficient, High Performance, Hybrid Variable Adders, Voltage Scaling

Abstract:

This paper presents a high speed carry skip adder (CSKA) structure yet brings down energy utilization contrasted with the existing one. The proficiency is improved that of the existing CSKA (Conv-CSKA) structure with updating the adder by applying the concatenation and incrementation plan. The AND-OR-Invert (AOI) and moreover OR-AND-Invert (OAI) logic gates are utilized for the skip logic as a replace to the multiplexer logic. The structure is acknowledged in both uniform (FSS) where at long last the speed and energy parameters of the adder are updated. At long last, a hybrid variable latency expansion of the proposed structure with an Brent-Kung parallel prefix adder, which brings down the power utilization without extensively affecting the speed, is presented. The proposed structures are evaluated by comparing their speed, power and energy parameters with those of different adders design by Verilog HDL and Simulated by Modelsim 6.4 c and Synthesized by Xilinx Design Suite 13.2 and proposed system implemented in FPGA Spartan 6 XC6SLX4 TQG-144 with a speed grade of -3.