Design and Simulation of a Novel 8T SRAM Cell for Low Power High Speed Applications
Author(s):
Sachin Kumar , Laxmi Narayan College of Technology, Bhopal, MP; Dr. Uma Shankar Kurmi, Laxmi Narayan College of Technology, Bhopal, MP
Keywords:
SRAM, Low Power VLSI, ASIC, Power Delay Product
Abstract:
Recently, the demand for portable communications has led to more and lower power ASIC (Application Specific Integrated Circuit) designs. It has been shown that power consumed during memory accesses accounts for a significant portion of the total power consumption in microprocessors, thus minimization of memory was as an important area of concern for today’s IC designers. A new design contain transmission gate as an access transistor .Simulation results of power dissipation, access time, current leakage, stability and power delay product of the proposed SRAM cell have been determined and compared with those of some other existing models of SRAM cell.
Other Details:
| Manuscript Id | : | IJSTEV4I3013
|
| Published in | : | Volume : 4, Issue : 3
|
| Publication Date | : | 01/10/2017
|
| Page(s) | : | 27-31
|
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